Phase detectors are normally suitable for comparing the phase angles of two signals (which are present at inputs of the phase detector) with one another, ascertaining a phase deviation which possibly exists between the two input signals and supplying a signal at their output, said signal being either proportional to or at least dependent on the phase difference between the input signals.
Phase detectors are used, for example, in phase locked loops in order to lock a signal (which is to be generated) at the desired frequency onto a reference signal source. Phase locked loops may be used to generate highly precise signals with high frequency stability by establishing reference to a reference source, for example a crystal oscillator. In this case, however, the frequency generated may be different from the reference frequency. A frequency divider is normally provided for this in the feedback path of the phase locked loop.
In order to achieve carrier modulation in digital communications applications as early as during generation of the frequency in the phase locked loop, developments of the phase locked loop provide a so-called fractional-N frequency divider in the feedback path from the oscillator to the phase detector, it being possible to use said frequency divider to set fractional divider ratios, averaged over one time interval. Phase locked loops of this type may be driven, for example, by a digitally coded modulation signal via so-called ΣΔ converters. The signal, which has been provided at the output by a phase detector and is dependent on the phase difference between the input signals, is normally passed to a charge pump output, which generates an upward or downward current, which in turn is normally integrated and, once converted into a corresponding control voltage, controls a controllable oscillator in such a manner that the phase difference at the input of the detector becomes smaller until it disappears.
Phase detectors of this type which can take into account not only a phase difference but also a frequency difference when comparing the input signals are referred to as phase-frequency detectors.
FIG. 3 shows a conventional phase detector arrangement. If, in the charge pump output stage 9′, 13′ of a phase detector 1, the upward and downward current sources 9′, 13′ do not supply an ideally identical current upon respective activation, a bend disadvantageously results at the origin of the family of characteristic curves of the charge pump phase detector unit, the average output current being plotted against the phase deviation of the input signals of the detector as characteristic curve in FIG. 4. However, since the origin, at which the characteristic curve bends, corresponds to the operating point of the phase detector, an undesirable nonlinearity results at the operating point. However, particularly in the case of the above-described fractional-N phase locked loops, fractional-N PLLs for short, a highly linear relationship between the output current of the phase detector and the phase difference between the input signals is of particularly significant importance for reliable operation of the circuit.
The document U.S. Pat. No. 6,002,273 specifies one option for shifting the described bend in the characteristic curve of the charge pump phase detector block out of the operating point of this circuit unit. For this purpose, in addition to the two current sources which are normally present and are intended for generating an upward current and a downward current, a third current source is provided there for the purpose of linearization. However, this additional, third current source in the output stage of the phase detector, the so-called charge pump, signifies additional complexity in the integration of the circuit, in particular an additional chip area and current requirement. However, this is undesirable particularly since phase locked loops are often used in mobile devices, for example radio plug-in cards, mobile telephones or cordless telephones, in which importance is attached to small dimensions, low fabrication costs in mass production and a low current requirement.
It is an object of the present invention to specify a circuit arrangement having a phase detector and also a phase locked loop having said circuit arrangement, which circuit arrangement and phase locked loop provide a highly linear characteristic curve between the output current of the phase detector and the phase difference between the input signals and at the same time may be implemented with relatively low complexity.